Semiconductor device having a high-K gate dielectric above an STI region

US9659928B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Andy Wei · Queensbury, US
• Roman Boschke · Dresden, DE
• Markus Forsberg · Dresden, DE

Key dates

• Filing date: Mar 11, 2015
• Grant date: May 23, 2017
• Expiry date: Jun 22, 2035

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/975
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.