Stacked transistors with different channel widths

US9660028B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Balasubramanian Pranatharthiharan · Watervliet, US
• John H. Zhang · Fishkill, US

Key dates

• Filing date: Oct 31, 2016
• Grant date: May 23, 2017
• Expiry date: Oct 31, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.