Semiconductor wafer and method
US9660037B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.