Programmable partitionable counter
US9667546B2 · kind B2 · utility
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17References
23Claims
0Family size
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Key dates
| Filing date | Jun 6, 2013 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | May 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.