Integrated circuit packaging system with coreless substrate and method of manufacture thereof
US9673171B1 · kind B1 · utility
0Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2014 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | May 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.