Three dimensional memory device with peripheral devices under dummy dielectric layer stack and method of making thereof
US9673213B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Feb 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a structure includes forming an in-process alternating stack including insulating layers and spacer material layers over a substrate, forming two sets of stepped surfaces by dividing the in-process alternating stack into a first alternating stack and a second alternating stack, the first alternating stack having first stepped surfaces and the second alternating stack having second stepped surfaces, forming at least one memory stack structure through the first alternating stack, each of the at least one memory stack structure including charge storage regions, a tunneling dielectric, and a semiconductor channel, replacing portions of the insulating layers in the first alternating stack with electrically conductive layers while leaving intact portions of the insulating layers in the second alternating stack, and forming a contact via structure through the second alternating stack to contact a peripheral semiconductor device under the second stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.