Three-dimensional memory devices containing memory block bridges
US9679906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Aug 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.