Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor

US9685457B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Ralf Illgen · Dresden, DE

Key dates

• Filing date: Jul 22, 2015
• Grant date: Jun 20, 2017
• Expiry date: Jul 22, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.