Inventor · Dresden, DE

Ralf Illgen

24Patents

4h-index

14Co-inventors

52Inventor score

Filing activity: Nov 23, 2009 → May 3, 2017

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9224840B2	Replacement gate FinFET structures with high mobility channel	Electricity	27	Active
US8912606B2	Integrated circuits having protruding source and drain regions and methods for forming integrated circuits	Electricity	14	Active
US9012277B2	In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices	Electricity	6	Active
US8835936B2	Source and drain doping using doped raised source and drain regions	Electricity	5	Active
US8536034B2	Methods of forming stressed silicon-carbon areas in an NMOS transistor	Electricity	4	Active
US9449972B1	Ferroelectric FinFET	Electricity	4	Active
US8835255B2	Method of forming a semiconductor structure including a vertical nanowire	Electricity	4	Active
US9023713B2	Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same	Electricity	4	Active
US8466018B2	Methods of forming a PMOS device with in situ doped epitaxial source/drain regions	Electricity	3	Active
US8580643B2	Threshold voltage adjustment in a Fin transistor by corner implantation	Electricity	3	Active
US8143133B2	Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes	Electricity	3	Active
US9899417B2	Semiconductor structure including a first transistor and a second transistor	Electricity	3	Active
US8338885B2	Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes	Electricity	3	Active
US10176859B2	Non-volatile transistor element including a buried ferroelectric material based storage mechanism	Electricity	2	Active
US9583240B2	Temperature independent resistor	Electricity	1	Active
US9269714B2	Device including a transistor having a stressed channel region and method for the formation thereof	Electricity	1	Active
US10056376B2	Ferroelectric FinFET	Electricity	1	Active
US8753969B2	Methods for fabricating MOS devices with stress memorization	Electricity	1	Active
US8476131B2	Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same	Electricity	0	Active
US8647951B2	Implantation of hydrogen to improve gate insulation layer-substrate interface	Electricity	0	Active
US8941187B2	Strain engineering in three-dimensional transistors based on strained isolation material	Electricity	0	Active
US9966466B2	Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof	Electricity	0	Active
US9685457B2	Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor	Electricity	0	Active
US8916928B2	Threshold voltage adjustment in a fin transistor by corner implantation	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.