Recovery from multiple data errors
US9690640B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Sep 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.