Storage scheme for built-in ECC operations
US9690650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2013 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Aug 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.