Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portions
US9691626B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Mar 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a pattern includes providing a structure having an etch mask layer disposed over a pattern layer disposed over a dielectric layer. Disposing first and second trench plugs having different material compositions in the etch mask layer, the first and second trench plugs overlaying gamma and beta block mask portions respectively of the pattern layer. Forming an array of self-aligned spacers disposed on sidewalls of mandrels, the spacers and mandrels defining alternating beta and gamma regions extending normally to the dielectric layer, the gamma region and beta regions extending though portions of the first and second trench plug respectively. Selectively etching the structure to remove any portion of the first trench plug within the beta region and any portion of the second trench plug within the gamma region. Selectively etching the structure to form a pattern in the pattern layer including the block mask portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.