Guillaume Bouche
157Patents
15h-index
165Co-inventors
89Inventor score
Filing activity: Jan 11, 2002 → Dec 29, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7684109B2 | Bragg mirror optimized for shear waves | Electricity | 263 | Active |
| US10014390B1 | Inner spacer formation for nanosheet field-effect transistors with tall suspensions | Electricity | 54 | Active |
| US9276064B1 | Fabricating stacked nanowire, field-effect transistors | Electricity | 38 | Active |
| US9362165B1 | 2D self-aligned via first process flow | Electricity | 35 | Active |
| US10026824B1 | Air-gap gate sidewall spacer and method | Electricity | 31 | Active |
| US7768364B2 | Bulk acoustic resonators with multi-layer electrodes | Electricity | 29 | Active |
| US9431512B2 | Methods of forming nanowire devices with spacers and the resulting devices | Electricity | 27 | Active |
| US6822329B2 | Integrated circuit connecting pad | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7966722B2 | Planarization method in the fabrication of a circuit | Emerging Cross-Sectional Technologies | 22 | Active |
| US9406775B1 | Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints | Electricity | 21 | Active |
| US9818641B1 | Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines | Electricity | 20 | Active |
| US9691775B1 | Combined SADP fins for semiconductor devices and methods of making the same | Electricity | 19 | Active |
| US9825031B1 | Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices | Electricity | 16 | Active |
| US7179392B2 | Method for forming a tunable piezoelectric microresonator | Emerging Cross-Sectional Technologies | 15 | Expired |
| US9805988B1 | Method of forming semiconductor structure including suspended semiconductor layer and resulting structure | Electricity | 15 | Active |
| US10566248B1 | Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar | Electricity | 14 | Active |
| US9852986B1 | Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit | Electricity | 14 | Active |
| US9818651B2 | Methods, apparatus and system for a passthrough-based architecture | Electricity | 14 | Active |
| US9818640B1 | Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines | Electricity | 14 | Active |
| US9455204B1 | 10 nm alternative N/P doped fin for SSRW scheme | Electricity | 13 | Active |
| US9812400B1 | Contact line having insulating spacer therein and method of forming same | Electricity | 13 | Active |
| US9899268B2 | Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device | Electricity | 12 | Active |
| US10002786B1 | Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts | Electricity | 12 | Active |
| US9306019B2 | Integrated circuits with nanowires and methods of manufacturing the same | Electricity | 11 | Active |
| US9425097B1 | Cut first alternative for 2D self-aligned via | Electricity | 11 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.