Patent · US Active

Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies

US9691669B1 · kind B1 · utility

2Cited by
2References
10Claims
0Family size

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Key dates

Filing dateAug 28, 2015
Grant dateJun 27, 2017
Priority date—
Expiry dateSep 25, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01B2210/56
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.