Method of testing a semiconductor-on-insulator structure and application of said test to the fabrication of such a structure
US9698063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2013 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Feb 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.