Two-dimensional process window improvement
US9703918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.