Gate height and spacer uniformity
US9704991B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/016
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.