On chip dynamic read level scan and error detection for nonvolatile storage
US9710325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Feb 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.