Stabilizing circuit
US9711190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2014 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Apr 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.