Vertical channel transistor-based semiconductor memory structure
US9711511B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Jun 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.