Memory with multiple write ports
US9721624B2 · kind B2 · utility
2Cited by
19References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.