Vertical field effect transistors with bottom contact metal directly beneath fins
US9721845B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments disclose a method for fabricating one or more vertical fin field-effect-transistors. In one embodiment, a structure is formed. The structure comprises a substrate, a source/drain layer, and a plurality of fins formed on the first source/drain layer. The source/drain layer comprises a first semiconductor layer, a sacrificial layer, and a second semiconductor layer. A bottom spacer layer is formed in contact with the second semiconductor layer and the plurality of fins. A gate structure is then formed. A dielectric layer is deposited in contact with at least the gate structure, the bottom spacer layer, and the second semiconductor layer. At least a portion of the dielectric layer and a portion of the second semiconductor are removed. This removal forms a trench exposing a portion of the sacrificial layer. The sacrificial layer is then removed forming a cavity. A contact material is deposited within the trench and the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.