Buffer layer for modulating Vt across devices

US9722045B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Bhupesh Chandra · Jersey City, US
• Viorel Ontalus · Danbury, US
• Timothy J. McArdle · Ballston Lake, US
• Paul Chang · Mahopac, US
• Claude Ortolland · Peekskill, US
• Judson R. Holt · Wappingers Falls, US

Key dates

• Filing date: Oct 23, 2015
• Grant date: Aug 1, 2017
• Expiry date: Oct 23, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/832
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.