3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same
US9728546B2 · kind B2 · utility
35Cited by
14References
12Claims
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Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Jun 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.