Semiconductor devices and methods for backside photo alignment
US9741612B2 · kind B2 · utility
1Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Feb 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.