Patent · US Active

Memory devices and systems having reduced bit line to drain select gate shorting and associated methods

US9741734B2 · kind B2 · utility

5Cited by
0References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 15, 2015
Grant dateAug 22, 2017
Priority date—
Expiry dateDec 15, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.