MRAM smart bit write algorithm with error correction parity bits
US9747159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Aug 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.