Reducing hot electron injection type of read disturb during read recovery phase in 3D memory
US9761320B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Dec 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and associated techniques for reducing read disturb of memory cells during the last phase of a sensing operation when all voltage signals are ramped down to a steady state voltage. In one aspect, the voltages of the source side word line, WL0, and an adjacent dummy word line, WLDS1, are ramped down after the voltages of remaining word lines are ramped down. This can occur regardless of whether WL0 is the selected word line which is programmed or read. The technique can be applied after the sensing which occurs in a read or program-verify operation. Another option involves elevating the voltage of the selected word line so that all word lines are ramped down from the same level, such as a read pass level. The techniques are particularly useful when the memory device includes an interface in the channel between epitaxial silicon and polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.