Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices
US9761495B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Feb 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.