Power MOSFET having planar channel, vertical current path, and top drain electrode
US9761702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.