Self-aligned source/drain junction for vertical field-effect transistor (FET) and method of forming the same

US9761728B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Xin Miao · Guilderland, US
• Wenyu Xu · Albany, US
• Chen Zhang · Guilderland, US

Key dates

• Filing date: May 25, 2016
• Grant date: Sep 12, 2017
• Expiry date: May 25, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85

Abstract

A method for manufacturing a semiconductor device includes forming a bottom source/drain region on a substrate, forming a semiconductor layer on the bottom source/drain region, patterning the semiconductor layer into a plurality of channel regions extending vertically with respect to the substrate, conformally forming a lower dielectric layer on the patterned semiconductor layer, forming a lower spacer layer on a portion of the lower dielectric layer, removing an exposed portion of the lower dielectric layer, forming a gate structure around the plurality of channel regions and on the lower spacer layer, and doping portions of the plurality of channel regions corresponding to the lower spacer layer, wherein the doping comprises diffusing a dopant from the lower dielectric layer into the portions of the plurality of channel regions.