Energy efficient processor core architecture for image processor
US9772852B2 · kind B2 · utility
10Cited by
30References
28Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 23, 2015 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jan 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N3/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.