Memory repair redundancy with array cache redundancy
US9773571B2 · kind B2 · utility
2Cited by
37References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2014 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.