System and method for providing an address cache for memory map learning
US9779020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2014 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.