Compensating for lithographic limitations in fabricating semiconductor interconnect structures
US9779943B2 · kind B2 · utility
4Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Feb 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.