Method and structure of forming self-aligned RMG gate for VFET
US9780208B1 · kind B1 · utility
49Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Jul 18, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jul 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.