Dynamic adjustment of memory cell digit line capacitance
US9786348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Apr 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2275
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.