Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing
US9793279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.