Integration of split gate flash memory array and logic devices
US9793280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.