Vertical vacuum channel transistor
US9793395B1 · kind B1 · utility
17Cited by
9References
6Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 6, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Oct 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.