Method of forming inner spacers on a nano-sheet/wire device
US9799748B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2017 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Jan 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a stack of semiconductor material layers above a substrate. The stack includes at least one first semiconductor material layer and at least one second semiconductor material layer. A first etching process is performed on the stack to define cavities. The cavities expose end portions of the first and second semiconductor material layers. Portions of the first semiconductor material layer are removed to define end recesses. A layer of insulating material is formed in the end recesses and at least partially fills the cavities. A second etching process is performed on the stack to remove end portions of the at least one second semiconductor material layer and to remove portions of the layer of insulating material in the cavities not disposed between the first and second semiconductor material layers so as to form inner spacers on ends of the at least one first semiconductor material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.