Patent · US Active

Memory cell with retention using resistive memory

US9805790B2 · kind B2 · utility

1Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Nathaniel J. August · Portland, US
Pulkit Jain · Hillsboro, US
Stefan Rusu · Sunnyvale, US
Fatih Hamzaoglu · Portland, US
Rangharajan Venkatesan · San Jose, US
Muhammad M. Khellah · Lake Oswego, US
Charles Augustine · Hillsboro, US
Carlos Tokunaga · Hillsboro, US
James W. Tschanz · Portland, US
Yih Wang · Portland, US

Key dates

Filing date	Dec 5, 2013
Grant date	Oct 31, 2017
Priority date	—
Expiry date	Dec 5, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/1693
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.