Semiconductor memory device and data erasing method
US9805804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | May 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.