Bottom source/drain silicidation for vertical field-effect transistor (FET)
US9805935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2015 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Feb 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.