Method of forming semiconductor structure including suspended semiconductor layer and resulting structure
US9805988B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Dec 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One aspect of the disclosure is directed to a method of forming a semiconductor structure including: forming a fin over a substrate within a device region, the fin including alternating layers of a sacrificial material and a semiconductor material, and including a lower channel region; forming a dopant-containing layer over the fin and the substrate; exposing an upper portion of the fin by removing the dopant-containing layer from the upper portion of the fin; removing the sacrificial material from the fin thereby suspending the semiconductor material within the fin between a pair of spacers and over the lower channel region of the fin; performing an anneal to drive in dopants from the dopant-containing layer to the lower channel region of the fin; and forming an active gate over the lower channel region of the fin and substantially surrounding the suspended semiconductor material over the lower channel region of the fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.