Methods of cutting gate structures on transistor devices
US9812365B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
Abstract
One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.