Hard mask etch and dielectric etch aware overlap for via and metal layers

US9817927B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Guo Xiang Ning · Ballston Lake, US
• Yuping Ren · Clifton Park, US
• David N. Power · Saratoga Springs, US
• Lalit Shokeen · Clifton Park, US
• Chin Teong Lim · Clifton Park, US
• Paul Ackmann · Gansevoort, US
• Xiang Hu · Shanghai, CN

Key dates

• Filing date: Aug 31, 2015
• Grant date: Nov 14, 2017
• Expiry date: Jun 14, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/398
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.