Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
US9818623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Mar 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.