Through-memory-level via structures for a three-dimensional memory device
US9818759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Sep 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.