Protection of memory interface
US9819657B2 · kind B2 · utility
3Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/0428
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.